mirror of
https://github.com/eclipse-threadx/levelx.git
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206 lines
9.0 KiB
C
206 lines
9.0 KiB
C
/**************************************************************************/
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/* */
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/* Copyright (c) Microsoft Corporation. All rights reserved. */
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/* */
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/* This software is licensed under the Microsoft Software License */
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/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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/* and in the root directory of this software. */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** LevelX Component */
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/** */
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/** NAND Flash */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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#define LX_SOURCE_CODE
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/* Disable ThreadX error checking. */
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#ifndef TX_DISABLE_ERROR_CHECKING
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#define TX_DISABLE_ERROR_CHECKING
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#endif
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/* Include necessary system files. */
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#include "lx_api.h"
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* _lx_nand_flash_extended_cache_enable PORTABLE C */
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/* 6.0 */
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/* AUTHOR */
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/* */
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/* William E. Lamie, Microsoft Corporation */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function sets up the extended NAND cache for block status, */
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/* page extra bytes, and page 0 contents. The routine will enable as */
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/* many cache capabilities as possible until the supplied memory is */
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/* exhausted. */
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/* */
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/* INPUT */
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/* */
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/* nand_flash NAND flash instance */
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/* memory Pointer to memory for caches */
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/* size Size of memory in bytes */
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/* */
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/* OUTPUT */
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/* */
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/* Completion Status */
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/* */
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/* CALLS */
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/* */
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/* None */
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/* */
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/* CALLED BY */
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/* */
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/* Internal LevelX */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 05-19-2020 William E. Lamie Initial Version 6.0 */
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/* */
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/**************************************************************************/
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UINT _lx_nand_flash_extended_cache_enable(LX_NAND_FLASH *nand_flash, VOID *memory, ULONG size)
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{
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UCHAR *working_ptr;
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ULONG adjust_size;
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ULONG i;
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/* Setup the working pointer. */
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working_ptr = (UCHAR *) memory;
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/* Check for a NULL pointer. If NULL, disable all the caches. */
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if (working_ptr == TX_NULL)
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{
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/* Disable all extended caches. */
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nand_flash -> lx_nand_flash_block_status_cache = TX_NULL;
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nand_flash -> lx_nand_flash_page_extra_bytes_cache = TX_NULL;
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nand_flash -> lx_nand_flash_page_0_cache = TX_NULL;
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/* Return success! */
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return(LX_SUCCESS);
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}
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/* Determine if there is not enough memory for the block status cache. */
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if (size < nand_flash -> lx_nand_flash_total_blocks)
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{
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/* Return an error since there is not enough memory for even the smallest
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cache. */
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return(LX_ERROR);
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}
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/* There is enough memory, setup the block status cache. */
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nand_flash -> lx_nand_flash_block_status_cache = working_ptr;
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/* Clear the block status cache. */
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for (i = 0; i < nand_flash -> lx_nand_flash_total_blocks; i++)
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{
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/* Clear the block status cache. */
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nand_flash -> lx_nand_flash_block_status_cache[i] = ((UCHAR) 0);
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}
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/* Calculate the size to adjust to achieve ULONG alignment. */
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adjust_size = nand_flash -> lx_nand_flash_total_blocks + ((ULONG) (sizeof(ULONG) - 1));
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adjust_size = (adjust_size/sizeof(ULONG)) * sizeof(ULONG);
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/* Adjust the size. */
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if (size >= adjust_size)
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{
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/* Subtract the aligned size. */
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size = size - adjust_size;
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}
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else
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{
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/* Just set size to 0. */
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size = 0;
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}
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/* Determine if there is enough memory for the page extra bytes cache for each page. */
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if (size >= (nand_flash -> lx_nand_flash_total_pages * sizeof(LX_NAND_PAGE_EXTRA_INFO)))
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{
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/* Yes, there is enough memory for the extra bytes cache. */
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/* First adjust the working pointer to the start of this memory. */
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working_ptr = working_ptr + adjust_size;
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/* Setup the pointer to page extra bytes cache. */
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nand_flash -> lx_nand_flash_page_extra_bytes_cache = (LX_NAND_PAGE_EXTRA_INFO *) working_ptr;
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/* Clear the page extra bytes cache. */
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for (i = 0; i < nand_flash -> lx_nand_flash_total_pages; i++)
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{
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/* Clear the block status cache. */
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nand_flash -> lx_nand_flash_page_extra_bytes_cache[i].lx_nand_page_extra_info_logical_sector = ((ULONG) 0);
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}
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/* Calculate the size to adjust to achieve ULONG alignment. */
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adjust_size = (nand_flash -> lx_nand_flash_total_pages * sizeof(LX_NAND_PAGE_EXTRA_INFO) + ((ULONG) (sizeof(ULONG) - 1)));
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adjust_size = (adjust_size/sizeof(ULONG)) * sizeof(ULONG);
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/* Adjust the size. */
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if (size >= adjust_size)
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{
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/* Subtract the aligned size. */
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size = size - adjust_size;
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}
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else
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{
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/* Just set size to 0. */
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size = 0;
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}
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}
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/* Determine if there is enough memory for the page 0 cache for each block. */
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if (size >= ((nand_flash -> lx_nand_flash_total_blocks * (nand_flash -> lx_nand_flash_pages_per_block + 1)) * sizeof(ULONG)))
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{
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/* Yes, there is enough memory for the page 0 cache. */
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/* First adjust the working pointer to the start of this memory. */
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working_ptr = working_ptr + adjust_size;
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/* Setup the pointer to page 0 cache. */
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nand_flash -> lx_nand_flash_page_0_cache = (ULONG *) working_ptr;
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/* Clear the page 0 cache. */
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for (i = 0; i < (nand_flash -> lx_nand_flash_total_blocks * (nand_flash -> lx_nand_flash_pages_per_block + 1)); i++)
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{
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/* Clear the block status cache. */
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nand_flash -> lx_nand_flash_page_0_cache[i] = ((ULONG) 0);
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}
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}
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/* Return success. */
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return(LX_SUCCESS);
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}
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