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添加GD32H7的CMake工程

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chentianya
2026-07-23 19:44:30 +08:00
commit d07f065b1c
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Firmware/CMSIS/GD/GD32H7xx/Include/gd32h7xx.h
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/*!
\file gd32h7xx.h
\brief general definitions for GD32H7xx
\version 2025-01-24, V1.4.0, firmware for GD32H7xx
*/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
* Copyright (c) 2025, GigaDevice Semiconductor Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef GD32H7XX_H
#define GD32H7XX_H
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (GD32H7XX)
#error "Please select the target GD32H7XX device used in your application (in gd32h7xx.h file)"
#endif /* undefine GD32H7XX tip */
/* define value of high speed crystal oscillator (HXTAL) in Hz */
#if !defined (HXTAL_VALUE)
#define HXTAL_VALUE ((uint32_t)25000000)
#endif /* high speed crystal oscillator value */
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
#if !defined (HXTAL_STARTUP_TIMEOUT)
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF)
#endif /* high speed crystal oscillator startup timeout */
/* define value of internal 64MHz RC oscillator (IRC64M) in Hz */
#if !defined (IRC64M_VALUE)
#define IRC64M_VALUE ((uint32_t)64000000)
#endif /* internal 64MHz RC oscillator value */
/* define startup timeout value of internal 64MHz RC oscillator (IRC64M) */
#if !defined (IRC64M_STARTUP_TIMEOUT)
#define IRC64M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 64MHz RC oscillator startup timeout */
/* define value of Low Power Internal 4Mhz RC oscillator (LPIRC4M) in Hz */
#if !defined (LPIRC4M_VALUE)
#define LPIRC4M_VALUE ((uint32_t)4000000)
#endif /* Low Power Internal 4Mhz RC oscillator value */
/* define startup timeout value of internal Low Power Internal 4Mhz RC oscillator (LPIRC4M) */
#if !defined (LPIRC4M_STARTUP_TIMEOUT)
#define LPIRC4M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* Low Power Internal 4Mhz RC oscillator startup timeout */
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
#if !defined (IRC48M_VALUE)
#define IRC48M_VALUE ((uint32_t)48000000)
#endif /* internal 48MHz RC oscillator value */
/* define startup timeout value of internal 48MHz RC oscillator (IRC48M) */
#if !defined (IRC48M_STARTUP_TIMEOUT)
#define IRC48M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 48MHz RC oscillator startup timeout */
/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
#if !defined (IRC32K_VALUE)
#define IRC32K_VALUE ((uint32_t)32000)
#endif /* internal 32KHz RC oscillator value */
/* define startup timeout value of internal 32KHz RC oscillator (IRC32K) */
#if !defined (IRC32K_STARTUP_TIMEOUT)
#define IRC32K_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 32KHz RC oscillator startup timeout */
/* define value of low speed crystal oscillator (LXTAL)in Hz */
#if !defined (LXTAL_VALUE)
#define LXTAL_VALUE ((uint32_t)32768)
#endif /* low speed crystal oscillator value */
/* define startup timeout value of low speed crystal oscillator (LXTAL) */
#if !defined (LXTAL_STARTUP_TIMEOUT)
#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x0FFFFFFF)
#endif /* low speed crystal oscillator startup timeout */
/* GD32H7xx firmware library version number V1.4.0 */
#define __GD32H7XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __GD32H7XX_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
#define __GD32H7XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __GD32H7XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __GD32H7XX_STDPERIPH_VERSION ((__GD32H7XX_STDPERIPH_VERSION_MAIN << 24)\
|(__GD32H7XX_STDPERIPH_VERSION_SUB1 << 16)\
|(__GD32H7XX_STDPERIPH_VERSION_SUB2 << 8)\
|(__GD32H7XX_STDPERIPH_VERSION_RC))
/* configuration of the Cortex-M7 processor and core peripherals */
#define __CM7_REV 0x0102U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
/* define interrupt number */
typedef enum IRQn {
/* Cortex-M7 processor exceptions numbers */
NonMaskableInt_IRQn = -14, /*!< non mask-able interrupt */
HardFault_IRQn = -13, /*!< hard-fault interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 memory management interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M7 bus fault interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M7 usage fault interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M7 sv call interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 debug monitor interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M7 pend sv interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M7 system tick interrupt */
/* interruput numbers */
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
VAVD_LVD_VOVD_IRQn = 1, /*!< AVD_LVD_OVD_IRQn through EXTI line detect interrupt */
TAMPER_STAMP_LXTAL_IRQn = 2, /*!< RTC tamper and timestamp interrupt/LXTAL clock stuck interrupt */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt */
FMC_IRQn = 4, /*!< FMC interrupt */
RCU_IRQn = 5, /*!< RCU interrupt */
EXTI0_IRQn = 6, /*!< EXTI line 0 */
EXTI1_IRQn = 7, /*!< EXTI line 1 */
EXTI2_IRQn = 8, /*!< EXTI line 2 */
EXTI3_IRQn = 9, /*!< EXTI line 3 */
EXTI4_IRQn = 10, /*!< EXTI line 4 */
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel 0 interrupt */
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel 1 interrupt */
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel 2 interrupt */
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel 3 interrupt */
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel 4 interrupt */
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel 5 interrupt */
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel 6 interrupt */
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 */
EXTI5_9_IRQn = 23, /*!< EXTI line 5 to 9 */
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger/commutation interrupt */
TIMER0_Channel_IRQn = 27, /*!< TIMER0 capture/compare interrupt */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_IRQn = 36, /*!< SPI1 interrupt */
USART0_IRQn = 37, /*!< USART0 global and wakeup interrupt */
USART1_IRQn = 38, /*!< USART1 global and wakeup interrupt */
USART2_IRQn = 39, /*!< USART2 global and wakeup interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI line 10 to 15 */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm interrupt */
TIMER7_BRK_IRQn = 43, /*!< TIMER7 Break global interrupt */
TIMER7_UP_IRQn = 44, /*!< TIMER7 Update global interrupt */
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 Trigger and Commutation global interrupt */
TIMER7_Channel_IRQn = 46, /*!< TIMER7 Capture Compare interrupt */
DMA0_Channel7_IRQn = 47, /*!< DMA0 channel 7 interrupt */
EXMC_IRQn = 48, /*!< EXMC interrupt */
SDIO0_IRQn = 49, /*!< SDMMC0 interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
SPI2_IRQn = 51, /*!< SPI2 interrupt */
UART3_IRQn = 52, /*!< UART3 interrupt */
UART4_IRQn = 53, /*!< UART4 interrupt */
TIMER5_DAC_UDR_IRQn = 54, /*!< TIMER5 global interrupt and DAC1/DAC0 underrun */
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
ENET0_IRQn = 61, /*!< ENET 0 interrupt */
ENET0_WKUP_IRQn = 62, /*!< ENET 0 wakeup through EXTI line interrupt */
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel 5 interrupt */
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel 6 interrupt */
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel 7 interrupt */
USART5_IRQn = 71, /*!< UART5 global and wakeup interrupt */
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
USBHS0_EP1_OUT_IRQn = 74, /*!< USBHS0 endpoint 1 out interrupt */
USBHS0_EP1_IN_IRQn = 75, /*!< USBHS0 endpoint 1 in interrupt */
USBHS0_WKUP_IRQn = 76, /*!< USBHS0 wakeup through EXTI line interrupt */
USBHS0_IRQn = 77, /*!< USBHS0 interrupt */
DCI_IRQn = 78, /*!< DCI interrupt */
CAU_IRQn = 79, /*!< CAU interrupt */
HAU_TRNG_IRQn = 80, /*!< HAU and TRNG interrupt */
FPU_IRQn = 81, /*!< FPU interrupt */
UART6_IRQn = 82, /*!< UART6 interrupt */
UART7_IRQn = 83, /*!< UART7 interrupt */
SPI3_IRQn = 84, /*!< SPI3 interrupt */
SPI4_IRQn = 85, /*!< SPI4 interrupt */
SPI5_IRQn = 86, /*!< SPI5 interrupt */
SAI0_IRQn = 87, /*!< SAI0 interrupt */
TLI_IRQn = 88, /*!< TLI interrupt */
TLI_ER_IRQn = 89, /*!< TLI error interrupt */
IPA_IRQn = 90, /*!< IPA interrupt */
SAI1_IRQn = 91, /*!< SAI1 interrupt */
OSPI0_IRQn = 92, /*!< OSPI0 global interrupt */
I2C3_EV_IRQn = 95, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 96, /*!< I2C3 error interrupt */
RSPDIF_IRQn = 97, /*!< RSPDIF global interrupt */
DMAMUX_OVR_IRQn = 102, /*!< DMAMUX overrun interrupt */
HPDF_INT0_IRQn = 110, /*!< HPDF filiter 0 interrupt */
HPDF_INT1_IRQn = 111, /*!< HPDF filiter 1 interrupt */
HPDF_INT2_IRQn = 112, /*!< HPDF filiter 2 interrupt */
HPDF_INT3_IRQn = 113, /*!< HPDF filiter 3 interrupt */
SAI2_IRQn = 114, /*!< SAI2 interrupt */
TIMER14_IRQn = 116, /*!< TIMER14 interrupt */
TIMER15_IRQn = 117, /*!< TIMER15 interrupt */
TIMER16_IRQn = 118, /*!< TIMER16 interrupt */
MDIO_IRQn = 120, /*!< MDIO interrupt */
MDMA_IRQn = 122, /*!< MDMA interrupt */
SDIO1_IRQn = 124, /*!< SDIO1 interrupt */
HWSEM_IRQn = 125, /*!< HWSEM interrupt */
ADC2_IRQn = 127, /*!< ADC2 interrupt */
CMP0_1_IRQn = 137, /*!< CMP0 and CMP1 interrupt */
CTC_IRQn = 144, /*!< CTC interrupt */
RAMECCMU_IRQn = 145, /*!< RAMECCMU interrupt */
OSPI1_IRQn = 150, /*!< OSPI1 interrupt */
RTDEC0_IRQn = 151, /*!< RTDEC0 interrupt */
RTDEC1_IRQn = 152, /*!< RTDEC1 interrupt */
FAC_IRQn = 153, /*!< FAC interrupt */
TMU_IRQn = 154, /*!< TMU interrupt */
TIMER22_IRQn = 161, /*!< TIMER22 interrupt */
TIMER23_IRQn = 162, /*!< TIMER23 interrupt */
TIMER30_IRQn = 163, /*!< TIMER30 interrupt */
TIMER31_IRQn = 164, /*!< TIMER31 interrupt */
TIMER40_IRQn = 165, /*!< TIMER40 interrupt */
TIMER41_IRQn = 166, /*!< TIMER41 interrupt */
TIMER42_IRQn = 167, /*!< TIMER42 interrupt */
TIMER43_IRQn = 168, /*!< TIMER43 interrupt */
TIMER44_IRQn = 169, /*!< TIMER44 interrupt */
TIMER50_IRQn = 170, /*!< TIMER50 interrupt */
TIMER51_IRQn = 171, /*!< TIMER51 interrupt */
USBHS1_EP1_OUT_IRQn = 172, /*!< USBHS1 endpoint 1 out interrupt */
USBHS1_EP1_IN_IRQn = 173, /*!< USBHS1 endpoint 1 in interrupt */
USBHS1_WKUP_IRQn = 174, /*!< USBHS1 wakeup through EXTI line interrupt */
USBHS1_IRQn = 175, /*!< USBHS1 interrupt */
ENET1_IRQn = 176, /*!< ENET1 interrupt */
ENET1_WKUP_IRQn = 177, /*!< ENET1 wakeup through EXTI line interrupt */
CAN0_WKUP_IRQn = 179, /*!< CAN 0 wakeup through EXTI line interrupt */
CAN0_Message_IRQn = 180, /*!< CAN 0 message buffer interrupt */
CAN0_Busoff_IRQn = 181, /*!< CAN 0 bus off / bus off done interrupt */
CAN0_Error_IRQn = 182, /*!< CAN 0 error interrupt */
CAN0_FastError_IRQn = 183, /*!< CAN 0 error in fast transmission interrupt */
CAN0_TEC_IRQn = 184, /*!< CAN 0 transmit warning interrupt */
CAN0_REC_IRQn = 185, /*!< CAN 0 receive warning interrupt */
CAN1_WKUP_IRQn = 186, /*!< CAN 1 wakeup through EXTI line interrupt */
CAN1_Message_IRQn = 187, /*!< CAN 1 message buffer interrupt */
CAN1_Busoff_IRQn = 188, /*!< CAN 1 bus off / bus off done interrupt */
CAN1_Error_IRQn = 189, /*!< CAN 1 error interrupt */
CAN1_FastError_IRQn = 190, /*!< CAN 1 error in fast transmission interrupt */
CAN1_TEC_IRQn = 191, /*!< CAN 1 transmit warning interrupt */
CAN1_REC_IRQn = 192, /*!< CAN 1 receive warning interrupt */
CAN2_WKUP_IRQn = 193, /*!< CAN 2 wakeup through EXTI line interrupt */
CAN2_Message_IRQn = 194, /*!< CAN 2 message buffer interrupt */
CAN2_Busoff_IRQn = 195, /*!< CAN 2 bus off / bus off done interrupt */
CAN2_Error_IRQn = 196, /*!< CAN 2 error interrupt */
CAN2_FastError_IRQn = 197, /*!< CAN 2 error in fast transmission interrupt */
CAN2_TEC_IRQn = 198, /*!< CAN 2 transmit warning interrupt */
CAN2_REC_IRQn = 199, /*!< CAN 2 receive warning interrupt */
EFUSE_IRQn = 200, /*!< EFUSE interrupt */
I2C0_WKUP_IRQn = 201, /*!< I2C 0 wakeup through EXTI line interrupt */
I2C1_WKUP_IRQn = 202, /*!< I2C 1 wakeup through EXTI line interrupt */
I2C2_WKUP_IRQn = 203, /*!< I2C 2 wakeup through EXTI line interrupt */
I2C3_WKUP_IRQn = 204, /*!< I2C 3 wakeup through EXTI line interrupt */
LPDTS_IRQn = 205, /*!< LPDTS interrupt */
LPDTS_WKUP_IRQn = 206, /*!< LPDTS wakeup through EXTI line interrupt */
TIMER0_DEC_IRQn = 207, /*!< TIMER0 DEC interrupt */
TIMER7_DEC_IRQn = 208, /*!< TIMER7 DEC interrupt */
TIMER1_DEC_IRQn = 209, /*!< TIMER1 DEC interrupt */
TIMER2_DEC_IRQn = 210, /*!< TIMER2 DEC interrupt */
TIMER3_DEC_IRQn = 211, /*!< TIMER3 DEC interrupt */
TIMER4_DEC_IRQn = 212, /*!< TIMER4 DEC interrupt */
TIMER22_DEC_IRQn = 213, /*!< TIMER22 DEC interrupt */
TIMER23_DEC_IRQn = 214, /*!< TIMER23 DEC interrupt */
TIMER30_DEC_IRQn = 215, /*!< TIMER30 DEC interrupt */
TIMER31_DEC_IRQn = 216, /*!< TIMER31 DEC interrupt */
} IRQn_Type;
/* includes */
#include "core_cm7.h"
#include "system_gd32h7xx.h"
#include <stdint.h>
/* enum definitions */
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
/* bit operations */
#define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr))
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x) ((uint32_t)((uint32_t)0x01U << (x)))
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
/* main flash and SRAM memory map */
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
#define SRAM_BASE ((uint32_t)0x24000000U) /*!< SRAM base address */
/* SRAM and peripheral base bit-band region */
#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
/* peripheral memory map */
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
#define APB3_BUS_BASE ((uint32_t)0x50000000U) /*!< apb3 base address */
#define APB4_BUS_BASE ((uint32_t)0x58000000U) /*!< apb4 base address */
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
#define AHB3_BUS_BASE ((uint32_t)0x51000000U) /*!< ahb3 base address */
#define AHB4_BUS_BASE ((uint32_t)0x58020000U) /*!< ahb4 base address */
/* advanced peripheral bus 1 memory map */
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
#define RSPDIF_BASE (APB1_BUS_BASE + 0x00004000U) /*!< RSPDIF base address */
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
#define CTC_BASE (APB1_BUS_BASE + 0x00008400U) /*!< CTC base address */
#define MDIO_BASE (APB1_BUS_BASE + 0x00009400U) /*!< MDIO base address */
/* advanced peripheral bus 2 memory map */
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
#define SAI_BASE (APB2_BUS_BASE + 0x00005800U) /*!< SAI base address */
#define HPDF_BASE (APB2_BUS_BASE + 0x00007000U) /*!< HPDF base address */
#define TRIGSEL_BASE (APB2_BUS_BASE + 0x00008400U) /*!< TRIGSEL base address */
#define EDOUT_BASE (APB2_BUS_BASE + 0x00008800U) /*!< EDOUT base address */
#define CAN_BASE (APB2_BUS_BASE + 0x0000A000U) /*!< CAN base address */
/* advanced peripheral bus 3 memory map */
#define TLI_BASE (APB3_BUS_BASE + 0x00001000U) /*!< TLI base address */
#define WWDGT_BASE (APB3_BUS_BASE + 0x00003000U) /*!< WWDGT base address */
/* advanced peripheral bus 4 memory map */
#define EXTI_BASE (APB4_BUS_BASE + 0x00000000U) /*!< EXTI base address */
#define SYSCFG_BASE (APB4_BUS_BASE + 0x00000400U) /*!< SYSCFG base address */
#define CMP_BASE (APB4_BUS_BASE + 0x00003800U) /*!< CMP base address */
#define VREF_BASE (APB4_BUS_BASE + 0x00003C00U) /*!< VREF base address */
#define RTC_BASE (APB4_BUS_BASE + 0x00004000U) /*!< CMP base address */
#define FWDGT_BASE (APB4_BUS_BASE + 0x00004800U) /*!< FWDGT base address */
#define PMU_BASE (APB4_BUS_BASE + 0x00005800U) /*!< PMU base address */
#define LPDTS_BASE (APB4_BUS_BASE + 0x00006800U) /*!< LPDTS base address */
/* advanced high performance bus 1 memory map */
#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
#define DMAMUX_BASE (AHB1_BUS_BASE + 0x00000800U) /*!< DMAMUX base address */
#define EFUSE_BASE (AHB1_BUS_BASE + 0x00002800U) /*!< EFUSE base address */
#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
/* advanced high performance bus 2 memory map */
#define DCI_BASE (AHB2_BUS_BASE + 0x00020000U) /*!< DCI base address */
#define CAU_BASE (AHB2_BUS_BASE + 0x00021000U) /*!< CAU base address */
#define HAU_BASE (AHB2_BUS_BASE + 0x00021400U) /*!< HAU base address */
#define TRNG_BASE (AHB2_BUS_BASE + 0x00021800U) /*!< TRNG base address */
#define SDIO_BASE (AHB2_BUS_BASE + 0x00022400U) /*!< SDIO base address */
#define CPDM_BASE (AHB2_BUS_BASE + 0x00022800U) /*!< CPDM base address */
#define RAMECCMU_BASE (AHB2_BUS_BASE + 0x00023000U) /*!< RAMECCMU base address */
#define TMU_BASE (AHB2_BUS_BASE + 0x00024400U) /*!< TMU base address */
#define FAC_BASE (AHB2_BUS_BASE + 0x00024800U) /*!< FAC base address */
/* advanced high performance bus 3 memory map */
#define AXIM_BASE (AHB3_BUS_BASE + 0x00000000U) /*!< AXIM base address */
#define MDMA_BASE (AHB3_BUS_BASE + 0x01000000U) /*!< MDMA base address */
#define IPA_BASE (AHB3_BUS_BASE + 0x01001000U) /*!< IPA base address */
#define FMC_BASE (AHB3_BUS_BASE + 0x01002000U) /*!< FMC base address */
#define FLEXRAMC_BASE (AHB3_BUS_BASE + 0x01003000U) /*!< FLEXRAMC base address */
#define EXMC_BASE (AHB3_BUS_BASE + 0x01004000U) /*!< EXMC base address */
#define OSPI_BASE (AHB3_BUS_BASE + 0x01005000U) /*!< OSPI base address */
#define OSPM_BASE (AHB3_BUS_BASE + 0x0100B400U) /*!< OSPM base address */
#define RTDEC_BASE (AHB3_BUS_BASE + 0x0100B800U) /*!< RTDEC base address */
/* advanced high performance bus 4 memory map */
#define GPIO_BASE (AHB4_BUS_BASE + 0x00000000U) /*!< GPIO base address */
#define RCU_BASE (AHB4_BUS_BASE + 0x00004400U) /*!< RCU base address */
#define CRC_BASE (AHB4_BUS_BASE + 0x00004C00U) /*!< CRC base address */
#define HWSEM_BASE (AHB4_BUS_BASE + 0x00006400U) /*!< HWSEM base address */
/* option byte and debug memory map */
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
#define DBG_BASE ((uint32_t)0xE00E1000U) /*!< DBG base address */
/* define marco USE_STDPERIPH_DRIVER */
#if !defined USE_STDPERIPH_DRIVER
#define USE_STDPERIPH_DRIVER
#endif
#ifdef USE_STDPERIPH_DRIVER
#include "gd32h7xx_libopt.h"
#endif /* USE_STDPERIPH_DRIVER */
#ifdef __cplusplus
}
#endif
#endif /* GD32H7XX_H */
Firmware/CMSIS/GD/GD32H7xx/Include/system_gd32h7xx.h
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/*!
\file system_gd32h7xx.h
\brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File for
gd32h7xx Device Series
*/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
* Copyright (c) 2025, GigaDevice Semiconductor Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef SYSTEM_GD32H7XX_H
#define SYSTEM_GD32H7XX_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* firmware version can be aquired by uncommenting the macro */
#define __FIRMWARE_VERSION_DEFINE
/* system clock frequency (core clock) */
extern uint32_t SystemCoreClock;
/* function declarations */
/* initialize the system and update the SystemCoreClock variable */
extern void SystemInit (void);
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
extern void SystemCoreClockUpdate (void);
#ifdef __FIRMWARE_VERSION_DEFINE
/* get firmware version */
extern uint32_t gd32h7xx_firmware_version_get(void);
#endif /* __FIRMWARE_VERSION_DEFINE */
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_GD32H7XX_H */
Firmware/CMSIS/GD/GD32H7xx/Source/ARM/startup_gd32h7xx.s
+729
View File
@@ -0,0 +1,729 @@
;/*!
; \file startup_gd32h7xx.s
; \brief start up file
; \version 2025-01-24, V1.4.0, firmware for GD32H7xx
;*/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; * Copyright (c) 2025, GigaDevice Semiconductor Inc.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x000000800
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; /* reset Vector Mapped to at Address 0 */
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; /* external interrupts handler */
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD VAVD_LVD_VOVD_IRQHandler ; 17:VAVD/LVD/VOVD through EXTI Line detect
DCD TAMPER_STAMP_LXTAL_IRQHandler ; 18:RTC Tamper and TimeStamp through EXTI Line detect, LXTAL clock security system interrupt
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup from EXTI interrupt
DCD FMC_IRQHandler ; 20:FMC global interrupt
DCD RCU_IRQHandler ; 21:RCU global interrupt
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_IRQHandler ; 52:SPI1
DCD USART0_IRQHandler ; 53:USART0 global and wakeup
DCD USART1_IRQHandler ; 54:USART1 global and wakeup
DCD USART2_IRQHandler ; 55:USART2 global and wakeup
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD 0 ; Reserved
DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break
DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update
DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel 7
DCD EXMC_IRQHandler ; 64:EXMC
DCD SDIO0_IRQHandler ; 65:SDIO0
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_IRQHandler ; 67:SPI2
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_UDR_IRQHandler ; 70:TIMER5 global interrupt and DAC1/DAC0 underrun error
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
DCD ENET0_IRQHandler ; 77:ENET0
DCD ENET0_WKUP_IRQHandler ; 78:ENET0 Wakeup through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
DCD USART5_IRQHandler ; 87:USART5 global and wakeup
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
DCD USBHS0_EP1_OUT_IRQHandler ; 90:USBHS0 Endpoint 1 Out
DCD USBHS0_EP1_IN_IRQHandler ; 91:USBHS0 Endpoint 1 in
DCD USBHS0_WKUP_IRQHandler ; 92:USBHS0 Wakeup through EXTI Line
DCD USBHS0_IRQHandler ; 93:USBHS0
DCD DCI_IRQHandler ; 94:DCI
DCD CAU_IRQHandler ; 95:CAU
DCD HAU_TRNG_IRQHandler ; 96:HAU and TRNG
DCD FPU_IRQHandler ; 97:FPU
DCD UART6_IRQHandler ; 98:UART6
DCD UART7_IRQHandler ; 99:UART7
DCD SPI3_IRQHandler ; 100:SPI3
DCD SPI4_IRQHandler ; 101:SPI4
DCD SPI5_IRQHandler ; 102:SPI5
DCD SAI0_IRQHandler ; 103:SAI0
DCD TLI_IRQHandler ; 104:TLI
DCD TLI_ER_IRQHandler ; 105:TLI Error
DCD IPA_IRQHandler ; 106:IPA
DCD SAI1_IRQHandler ; 107:SAI1
DCD OSPI0_IRQHandler ; 108:OSPI0
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; 111:I2C3 Event
DCD I2C3_ER_IRQHandler ; 112:I2C3 Error
DCD RSPDIF_IRQHandler ; 113:RSPDIF
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMAMUX_OVR_IRQHandler ; 118:DMAMUX Overrun interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD HPDF_INT0_IRQHandler ; 126:HPDF global interrupt 0
DCD HPDF_INT1_IRQHandler ; 127:HPDF global interrupt 1
DCD HPDF_INT2_IRQHandler ; 128:HPDF global interrupt 2
DCD HPDF_INT3_IRQHandler ; 129:HPDF global interrupt 3
DCD SAI2_IRQHandler ; 130:SAI2 global interrupt
DCD 0 ; Reserved
DCD TIMER14_IRQHandler ; 132:TIMER14
DCD TIMER15_IRQHandler ; 133:TIMER15
DCD TIMER16_IRQHandler ; 134:TIMER16
DCD 0 ; Reserved
DCD MDIO_IRQHandler ; 136:MDIO
DCD 0 ; Reserved
DCD MDMA_IRQHandler ; 138:MDMA
DCD 0 ; Reserved
DCD SDIO1_IRQHandler ; 140:SDIO1
DCD HWSEM_IRQHandler ; 141:HWSEM
DCD 0 ; Reserved
DCD ADC2_IRQHandler ; 143:ADC2
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CMP0_1_IRQHandler ; 153:CMP0 and CMP1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CTC_IRQHandler ; 160:Clock Recovery System
DCD RAMECCMU_IRQHandler ; 161:RAMECCMU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD OSPI1_IRQHandler ; 166:OSPI1
DCD RTDEC0_IRQHandler ; 167:RTDEC0
DCD RTDEC1_IRQHandler ; 168:RTDEC1
DCD FAC_IRQHandler ; 169:FAC
DCD TMU_IRQHandler ; 170:TMU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIMER22_IRQHandler ; 177:TIMER22
DCD TIMER23_IRQHandler ; 178:TIMER23
DCD TIMER30_IRQHandler ; 179:TIMER30
DCD TIMER31_IRQHandler ; 180:TIMER31
DCD TIMER40_IRQHandler ; 181:TIMER40
DCD TIMER41_IRQHandler ; 182:TIMER41
DCD TIMER42_IRQHandler ; 183:TIMER42
DCD TIMER43_IRQHandler ; 184:TIMER43
DCD TIMER44_IRQHandler ; 185:TIMER44
DCD TIMER50_IRQHandler ; 186:TIMER50
DCD TIMER51_IRQHandler ; 187:TIMER51
DCD USBHS1_EP1_OUT_IRQHandler ; 188:USBHS1 endpoint 1 out
DCD USBHS1_EP1_IN_IRQHandler ; 189:USBHS1 endpoint 1 in
DCD USBHS1_WKUP_IRQHandler ; 190:USBHS1 wakeup
DCD USBHS1_IRQHandler ; 191:USBHS1
DCD ENET1_IRQHandler ; 192:ENET1
DCD ENET1_WKUP_IRQHandler ; 193:ENET1 wakeup
DCD 0 ; Reserved
DCD CAN0_WKUP_IRQHandler ; 195:CAN0 wakeup
DCD CAN0_Message_IRQHandler ; 196:CAN0 interrupt for message buffer
DCD CAN0_Busoff_IRQHandler ; 197:CAN0 interrupt for Bus off / Bus off done
DCD CAN0_Error_IRQHandler ; 198:CAN0 interrupt for Error
DCD CAN0_FastError_IRQHandler ; 199:CAN0 interrupt for Error in fast transmission
DCD CAN0_TEC_IRQHandler ; 200:CAN0 interrupt for Transmit warning
DCD CAN0_REC_IRQHandler ; 201:CAN0 interrupt for Receive warning
DCD CAN1_WKUP_IRQHandler ; 202:CAN1 wakeup
DCD CAN1_Message_IRQHandler ; 203:CAN1 interrupt for message buffer
DCD CAN1_Busoff_IRQHandler ; 204:CAN1 interrupt for Bus off / Bus off done
DCD CAN1_Error_IRQHandler ; 205:CAN1 interrupt for Error
DCD CAN1_FastError_IRQHandler ; 206:CAN1 interrupt for Error in fast transmission
DCD CAN1_TEC_IRQHandler ; 207:CAN1 interrupt for Transmit warning
DCD CAN1_REC_IRQHandler ; 208:CAN1 interrupt for Receive warning
DCD CAN2_WKUP_IRQHandler ; 209:CAN2 wakeup
DCD CAN2_Message_IRQHandler ; 210:CAN2 interrupt for message buffer
DCD CAN2_Busoff_IRQHandler ; 211:CAN2 interrupt for Bus off / Bus off done
DCD CAN2_Error_IRQHandler ; 212:CAN2 interrupt for Error
DCD CAN2_FastError_IRQHandler ; 213:CAN2 interrupt for Error in fast transmission
DCD CAN2_TEC_IRQHandler ; 214:CAN2 interrupt for Transmit warning
DCD CAN2_REC_IRQHandler ; 215:CAN2 interrupt for Receive warning
DCD EFUSE_IRQHandler ; 216:EFUSE
DCD I2C0_WKUP_IRQHandler ; 217:I2C0 wakeup
DCD I2C1_WKUP_IRQHandler ; 218:I2C1 wakeup
DCD I2C2_WKUP_IRQHandler ; 219:I2C2 wakeup
DCD I2C3_WKUP_IRQHandler ; 220:I2C3 wakeup
DCD LPDTS_IRQHandler ; 221:LPDTS
DCD LPDTS_WKUP_IRQHandler ; 222:LPDTS wakeup
DCD TIMER0_DEC_IRQHandler ; 223:TIMER0 DEC
DCD TIMER7_DEC_IRQHandler ; 224:TIMER7 DEC
DCD TIMER1_DEC_IRQHandler ; 225:TIMER1 DEC
DCD TIMER2_DEC_IRQHandler ; 226:TIMER2 DEC
DCD TIMER3_DEC_IRQHandler ; 227:TIMER3 DEC
DCD TIMER4_DEC_IRQHandler ; 228:TIMER4 DEC
DCD TIMER22_DEC_IRQHandler ; 229:TIMER22 DEC
DCD TIMER23_DEC_IRQHandler ; 230:TIMER23 DEC
DCD TIMER30_DEC_IRQHandler ; 231:TIMER30 DEC
DCD TIMER31_DEC_IRQHandler ; 232:TIMER31 DEC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;/* reset Handler */
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
IMPORT |Image$$RW_IRAM1$$RW$$Base|
LDR R0, =|Image$$RW_IRAM1$$RW$$Base|
ADD R1, R0, #0x8000
LDR R2, =0x0
MEM_INIT STRD R2, R2, [ R0 ] , #8
CMP R0, R1
BNE MEM_INIT
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;/* dummy Exception Handlers */
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
; /* external interrupts handler */
EXPORT WWDGT_IRQHandler [WEAK]
EXPORT VAVD_LVD_VOVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_LXTAL_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT RCU_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA0_Channel0_IRQHandler [WEAK]
EXPORT DMA0_Channel1_IRQHandler [WEAK]
EXPORT DMA0_Channel2_IRQHandler [WEAK]
EXPORT DMA0_Channel3_IRQHandler [WEAK]
EXPORT DMA0_Channel4_IRQHandler [WEAK]
EXPORT DMA0_Channel5_IRQHandler [WEAK]
EXPORT DMA0_Channel6_IRQHandler [WEAK]
EXPORT ADC0_1_IRQHandler [WEAK]
EXPORT EXTI5_9_IRQHandler [WEAK]
EXPORT TIMER0_BRK_IRQHandler [WEAK]
EXPORT TIMER0_UP_IRQHandler [WEAK]
EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
EXPORT TIMER0_Channel_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT I2C0_EV_IRQHandler [WEAK]
EXPORT I2C0_ER_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI10_15_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIMER7_BRK_IRQHandler [WEAK]
EXPORT TIMER7_UP_IRQHandler [WEAK]
EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK]
EXPORT TIMER7_Channel_IRQHandler [WEAK]
EXPORT DMA0_Channel7_IRQHandler [WEAK]
EXPORT EXMC_IRQHandler [WEAK]
EXPORT SDIO0_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT TIMER5_DAC_UDR_IRQHandler [WEAK]
EXPORT TIMER6_IRQHandler [WEAK]
EXPORT DMA1_Channel0_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT ENET0_IRQHandler [WEAK]
EXPORT ENET0_WKUP_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT USART5_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT USBHS0_EP1_OUT_IRQHandler [WEAK]
EXPORT USBHS0_EP1_IN_IRQHandler [WEAK]
EXPORT USBHS0_WKUP_IRQHandler [WEAK]
EXPORT USBHS0_IRQHandler [WEAK]
EXPORT DCI_IRQHandler [WEAK]
EXPORT CAU_IRQHandler [WEAK]
EXPORT HAU_TRNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART6_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SAI0_IRQHandler [WEAK]
EXPORT TLI_IRQHandler [WEAK]
EXPORT TLI_ER_IRQHandler [WEAK]
EXPORT IPA_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT OSPI0_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT RSPDIF_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT HPDF_INT0_IRQHandler [WEAK]
EXPORT HPDF_INT1_IRQHandler [WEAK]
EXPORT HPDF_INT2_IRQHandler [WEAK]
EXPORT HPDF_INT3_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT TIMER14_IRQHandler [WEAK]
EXPORT TIMER15_IRQHandler [WEAK]
EXPORT TIMER16_IRQHandler [WEAK]
EXPORT MDIO_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT SDIO1_IRQHandler [WEAK]
EXPORT HWSEM_IRQHandler [WEAK]
EXPORT ADC2_IRQHandler [WEAK]
EXPORT CMP0_1_IRQHandler [WEAK]
EXPORT CTC_IRQHandler [WEAK]
EXPORT RAMECCMU_IRQHandler [WEAK]
EXPORT OSPI1_IRQHandler [WEAK]
EXPORT RTDEC0_IRQHandler [WEAK]
EXPORT RTDEC1_IRQHandler [WEAK]
EXPORT FAC_IRQHandler [WEAK]
EXPORT TMU_IRQHandler [WEAK]
EXPORT TIMER22_IRQHandler [WEAK]
EXPORT TIMER23_IRQHandler [WEAK]
EXPORT TIMER30_IRQHandler [WEAK]
EXPORT TIMER31_IRQHandler [WEAK]
EXPORT TIMER40_IRQHandler [WEAK]
EXPORT TIMER41_IRQHandler [WEAK]
EXPORT TIMER42_IRQHandler [WEAK]
EXPORT TIMER43_IRQHandler [WEAK]
EXPORT TIMER44_IRQHandler [WEAK]
EXPORT TIMER50_IRQHandler [WEAK]
EXPORT TIMER51_IRQHandler [WEAK]
EXPORT USBHS1_EP1_OUT_IRQHandler [WEAK]
EXPORT USBHS1_EP1_IN_IRQHandler [WEAK]
EXPORT USBHS1_WKUP_IRQHandler [WEAK]
EXPORT USBHS1_IRQHandler [WEAK]
EXPORT ENET1_IRQHandler [WEAK]
EXPORT ENET1_WKUP_IRQHandler [WEAK]
EXPORT CAN0_WKUP_IRQHandler [WEAK]
EXPORT CAN0_Message_IRQHandler [WEAK]
EXPORT CAN0_Busoff_IRQHandler [WEAK]
EXPORT CAN0_Error_IRQHandler [WEAK]
EXPORT CAN0_FastError_IRQHandler [WEAK]
EXPORT CAN0_TEC_IRQHandler [WEAK]
EXPORT CAN0_REC_IRQHandler [WEAK]
EXPORT CAN1_WKUP_IRQHandler [WEAK]
EXPORT CAN1_Message_IRQHandler [WEAK]
EXPORT CAN1_Busoff_IRQHandler [WEAK]
EXPORT CAN1_Error_IRQHandler [WEAK]
EXPORT CAN1_FastError_IRQHandler [WEAK]
EXPORT CAN1_TEC_IRQHandler [WEAK]
EXPORT CAN1_REC_IRQHandler [WEAK]
EXPORT CAN2_WKUP_IRQHandler [WEAK]
EXPORT CAN2_Message_IRQHandler [WEAK]
EXPORT CAN2_Busoff_IRQHandler [WEAK]
EXPORT CAN2_Error_IRQHandler [WEAK]
EXPORT CAN2_FastError_IRQHandler [WEAK]
EXPORT CAN2_TEC_IRQHandler [WEAK]
EXPORT CAN2_REC_IRQHandler [WEAK]
EXPORT EFUSE_IRQHandler [WEAK]
EXPORT I2C0_WKUP_IRQHandler [WEAK]
EXPORT I2C1_WKUP_IRQHandler [WEAK]
EXPORT I2C2_WKUP_IRQHandler [WEAK]
EXPORT I2C3_WKUP_IRQHandler [WEAK]
EXPORT LPDTS_IRQHandler [WEAK]
EXPORT LPDTS_WKUP_IRQHandler [WEAK]
EXPORT TIMER0_DEC_IRQHandler [WEAK]
EXPORT TIMER7_DEC_IRQHandler [WEAK]
EXPORT TIMER1_DEC_IRQHandler [WEAK]
EXPORT TIMER2_DEC_IRQHandler [WEAK]
EXPORT TIMER3_DEC_IRQHandler [WEAK]
EXPORT TIMER4_DEC_IRQHandler [WEAK]
EXPORT TIMER22_DEC_IRQHandler [WEAK]
EXPORT TIMER23_DEC_IRQHandler [WEAK]
EXPORT TIMER30_DEC_IRQHandler [WEAK]
EXPORT TIMER31_DEC_IRQHandler [WEAK]
;/* external interrupts handler */
WWDGT_IRQHandler
VAVD_LVD_VOVD_IRQHandler
TAMPER_STAMP_LXTAL_IRQHandler
RTC_WKUP_IRQHandler
FMC_IRQHandler
RCU_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA0_Channel0_IRQHandler
DMA0_Channel1_IRQHandler
DMA0_Channel2_IRQHandler
DMA0_Channel3_IRQHandler
DMA0_Channel4_IRQHandler
DMA0_Channel5_IRQHandler
DMA0_Channel6_IRQHandler
ADC0_1_IRQHandler
EXTI5_9_IRQHandler
TIMER0_BRK_IRQHandler
TIMER0_UP_IRQHandler
TIMER0_TRG_CMT_IRQHandler
TIMER0_Channel_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
I2C0_EV_IRQHandler
I2C0_ER_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI10_15_IRQHandler
RTC_Alarm_IRQHandler
TIMER7_BRK_IRQHandler
TIMER7_UP_IRQHandler
TIMER7_TRG_CMT_IRQHandler
TIMER7_Channel_IRQHandler
DMA0_Channel7_IRQHandler
EXMC_IRQHandler
SDIO0_IRQHandler
TIMER4_IRQHandler
SPI2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
TIMER5_DAC_UDR_IRQHandler
TIMER6_IRQHandler
DMA1_Channel0_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
ENET0_IRQHandler
ENET0_WKUP_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
USART5_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
USBHS0_EP1_OUT_IRQHandler
USBHS0_EP1_IN_IRQHandler
USBHS0_WKUP_IRQHandler
USBHS0_IRQHandler
DCI_IRQHandler
CAU_IRQHandler
HAU_TRNG_IRQHandler
FPU_IRQHandler
UART6_IRQHandler
UART7_IRQHandler
SPI3_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SAI0_IRQHandler
TLI_IRQHandler
TLI_ER_IRQHandler
IPA_IRQHandler
SAI1_IRQHandler
OSPI0_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
RSPDIF_IRQHandler
DMAMUX_OVR_IRQHandler
HPDF_INT0_IRQHandler
HPDF_INT1_IRQHandler
HPDF_INT2_IRQHandler
HPDF_INT3_IRQHandler
SAI2_IRQHandler
TIMER14_IRQHandler
TIMER15_IRQHandler
TIMER16_IRQHandler
MDIO_IRQHandler
MDMA_IRQHandler
SDIO1_IRQHandler
HWSEM_IRQHandler
ADC2_IRQHandler
CMP0_1_IRQHandler
CTC_IRQHandler
RAMECCMU_IRQHandler
OSPI1_IRQHandler
RTDEC0_IRQHandler
RTDEC1_IRQHandler
FAC_IRQHandler
TMU_IRQHandler
TIMER22_IRQHandler
TIMER23_IRQHandler
TIMER30_IRQHandler
TIMER31_IRQHandler
TIMER40_IRQHandler
TIMER41_IRQHandler
TIMER42_IRQHandler
TIMER43_IRQHandler
TIMER44_IRQHandler
TIMER50_IRQHandler
TIMER51_IRQHandler
USBHS1_EP1_OUT_IRQHandler
USBHS1_EP1_IN_IRQHandler
USBHS1_WKUP_IRQHandler
USBHS1_IRQHandler
ENET1_IRQHandler
ENET1_WKUP_IRQHandler
CAN0_WKUP_IRQHandler
CAN0_Message_IRQHandler
CAN0_Busoff_IRQHandler
CAN0_Error_IRQHandler
CAN0_FastError_IRQHandler
CAN0_TEC_IRQHandler
CAN0_REC_IRQHandler
CAN1_WKUP_IRQHandler
CAN1_Message_IRQHandler
CAN1_Busoff_IRQHandler
CAN1_Error_IRQHandler
CAN1_FastError_IRQHandler
CAN1_TEC_IRQHandler
CAN1_REC_IRQHandler
CAN2_WKUP_IRQHandler
CAN2_Message_IRQHandler
CAN2_Busoff_IRQHandler
CAN2_Error_IRQHandler
CAN2_FastError_IRQHandler
CAN2_TEC_IRQHandler
CAN2_REC_IRQHandler
EFUSE_IRQHandler
I2C0_WKUP_IRQHandler
I2C1_WKUP_IRQHandler
I2C2_WKUP_IRQHandler
I2C3_WKUP_IRQHandler
LPDTS_IRQHandler
LPDTS_WKUP_IRQHandler
TIMER0_DEC_IRQHandler
TIMER7_DEC_IRQHandler
TIMER1_DEC_IRQHandler
TIMER2_DEC_IRQHandler
TIMER3_DEC_IRQHandler
TIMER4_DEC_IRQHandler
TIMER22_DEC_IRQHandler
TIMER23_DEC_IRQHandler
TIMER30_DEC_IRQHandler
TIMER31_DEC_IRQHandler
B .
ENDP
ALIGN
; user Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
Firmware/CMSIS/GD/GD32H7xx/Source/GCC/startup_gd32h7xx.S
+830
View File
@@ -0,0 +1,830 @@
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global Default_Handler
/* necessary symbols defined in linker script to initialize data */
.word _sidata
.word _sdata
.word _edata
.word _sbss
.word _ebss
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
/* reset Handler */
Reset_Handler:
LDR r1, =0x24000000
LDR r2, =0x80000 /* 512K AXI SRAM */
MOV r0, #0x00
SRAM_INIT:
STM r1!, {r0}
SUBS r2, r2, #4
CMP r2, #0x00
BNE SRAM_INIT
movs r1, #0
b DataInit
CopyData:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
DataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyData
ldr r2, =_sbss
b Zerobss
FillZerobss:
movs r3, #0
str r3, [r2], #4
Zerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call SystemInit function */
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/*Call the main function */
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
.section .vectors,"a",%progbits
.global __gVectors
__gVectors:
.word _sp /* Top of Stack */
.word Reset_Handler /* Reset Handler */
.word NMI_Handler /* NMI Handler */
.word HardFault_Handler /* Hard Fault Handler */
.word MemManage_Handler /* MPU Fault Handler */
.word BusFault_Handler /* Bus Fault Handler */
.word UsageFault_Handler /* Usage Fault Handler */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SVC_Handler /* SVCall Handler */
.word DebugMon_Handler /* Debug Monitor Handler */
.word 0 /* Reserved */
.word PendSV_Handler /* PendSV Handler */
.word SysTick_Handler /* SysTick Handler */
/* External interrupts handler */
.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
.word AVD_LVD_OVD_IRQHandler /* Vector Number 17,AVD/LVD/OVD through EXTI Line detect */
.word TAMPER_STAMP_LXTAL_IRQHandler /* Vector Number 18,RTC Tamper and TimeStamp through EXTI Line detect, LXTAL clock security system interrupt */
.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup from EXTI interrupt */
.word FMC_IRQHandler /* Vector Number 20,FMC global interrupt */
.word RCU_IRQHandler /* Vector Number 21,RCU global interrupt */
.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel 0 */
.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel 1 */
.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel 2 */
.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel 3 */
.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel 4 */
.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel 5 */
.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel 6 */
.word ADC0_1_IRQHandler /* Vector Number 34,ADC0 and ADC1 interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
.word TIMER0_BRK_IRQHandler /* Vector Number 40,TIMER0 Break */
.word TIMER0_UP_IRQHandler /* Vector Number 41,TIMER0 Update */
.word TIMER0_TRG_CMT_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation */
.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Capture Compare */
.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
.word USART0_IRQHandler /* Vector Number 53,USART0 global and wakeup */
.word USART1_IRQHandler /* Vector Number 54,USART1 global and wakeup */
.word USART2_IRQHandler /* Vector Number 55,USART2 global and wakeup */
.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
.word 0 /* Reserved */
.word TIMER7_BRK_IRQHandler /* Vector Number 59,TIMER7 Break */
.word TIMER7_UP_IRQHandler /* Vector Number 60,TIMER7 Update */
.word TIMER7_TRG_CMT_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation */
.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */
.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel 7 */
.word EXMC_IRQHandler /* Vector Number 64,EXMC */
.word SDIO0_IRQHandler /* Vector Number 65,SDIO0 */
.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
.word UART3_IRQHandler /* Vector Number 68,UART3 */
.word UART4_IRQHandler /* Vector Number 69,UART4 */
.word TIMER5_DAC_UDR_IRQHandler /* Vector Number 70,TIMER5 global interrupt and DAC1/DAC0 underrun error */
.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
.word ENET0_IRQHandler /* Vector Number 77,Ethernet0 */
.word ENET0_WKUP_IRQHandler /* Vector Number 78,Ethernet0 Wakeup through EXTI Line */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
.word USART5_IRQHandler /* Vector Number 87,USART5 global and wakeup */
.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
.word USBHS0_EP1_OUT_IRQHandler /* Vector Number 90,USBHS0 Endpoint 1 Out */
.word USBHS0_EP1_IN_IRQHandler /* Vector Number 91,USBHS0 Endpoint 1 in */
.word USBHS0_WKUP_IRQHandler /* Vector Number 92,USBHS0 Wakeup through EXTI Line */
.word USBHS0_IRQHandler /* Vector Number 93,USBHS0 */
.word DCI_IRQHandler /* Vector Number 94,DCI */
.word CAU_IRQHandler /* Vector Number 95,CAU */
.word HAU_TRNG_IRQHandler /* Vector Number 96,HAU and TRNG */
.word FPU_IRQHandler /* Vector Number 97,FPU */
.word UART6_IRQHandler /* Vector Number 98,UART6 */
.word UART7_IRQHandler /* Vector Number 99,UART7 */
.word SPI3_IRQHandler /* Vector Number 100,SPI3 */
.word SPI4_IRQHandler /* Vector Number 101,SPI4 */
.word SPI5_IRQHandler /* Vector Number 102,SPI5 */
.word SAI0_IRQHandler /* Vector Number 103,SAI0 */
.word TLI_IRQHandler /* Vector Number 104,TLI */
.word TLI_ER_IRQHandler /* Vector Number 105,TLI Error */
.word IPA_IRQHandler /* Vector Number 106,IPA */
.word SAI1_IRQHandler /* Vector Number 107,SAI1 */
.word OSPI0_IRQHandler /* Vector Number 108,OSPI0 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word I2C3_EV_IRQHandler /* Vector Number 111,I2C3 Event */
.word I2C3_ER_IRQHandler /* Vector Number 112,I2C3 Error */
.word RSPDIF_IRQHandler /* Vector Number 113,RSPDIF */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMAMUX_OVR_IRQHandler /* Vector Number 118,DMAMUX Overrun interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word HPDF_INT0_IRQHandler /* Vector Number 126,HPDF global interrupt 0 */
.word HPDF_INT1_IRQHandler /* Vector Number 127,HPDF global interrupt 1 */
.word HPDF_INT2_IRQHandler /* Vector Number 128,HPDF global interrupt 2 */
.word HPDF_INT3_IRQHandler /* Vector Number 129,HPDF global interrupt 3 */
.word SAI2_IRQHandler /* Vector Number 130,SAI2 global interrupt */
.word 0 /* Reserved */
.word TIMER14_IRQHandler /* Vector Number 132,TIMER14 */
.word TIMER15_IRQHandler /* Vector Number 133,TIMER15 */
.word TIMER16_IRQHandler /* Vector Number 134,TIMER16 */
.word 0 /* Reserved */
.word MDIO_IRQHandler /* Vector Number 136,MDIO */
.word 0 /* Reserved */
.word MDMA_IRQHandler /* Vector Number 138,MDMA */
.word 0 /* Reserved */
.word SDIO1_IRQHandler /* Vector Number 140,SDIO1 */
.word HWSEM_IRQHandler /* Vector Number 141,HWSEM */
.word 0 /* Reserved */
.word ADC2_IRQHandler /* Vector Number 143,ADC2 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word CMP0_1_IRQHandler /* Vector Number 153,CMP0 and CMP1 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word CTC_IRQHandler /* Vector Number 160,Clock Recovery System */
.word RAMECCMU_IRQHandler /* Vector Number 161,RAMECCMU */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OSPI1_IRQHandler /* Vector Number 166,OSPI1 */
.word RTDEC0_IRQHandler /* Vector Number 167,RTDEC0 */
.word RTDEC1_IRQHandler /* Vector Number 168,RTDEC1 */
.word FAC_IRQHandler /* Vector Number 169,FAC */
.word TMU_IRQHandler /* Vector Number 170,TMU */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word TIMER22_IRQHandler /* Vector Number 177,TIMER22 */
.word TIMER23_IRQHandler /* Vector Number 178,TIMER23 */
.word TIMER30_IRQHandler /* Vector Number 179,TIMER30 */
.word TIMER31_IRQHandler /* Vector Number 180,TIMER31 */
.word TIMER40_IRQHandler /* Vector Number 181,TIMER40 */
.word TIMER41_IRQHandler /* Vector Number 182,TIMER41 */
.word TIMER42_IRQHandler /* Vector Number 183,TIMER42 */
.word TIMER43_IRQHandler /* Vector Number 184,TIMER43 */
.word TIMER44_IRQHandler /* Vector Number 185,TIMER44 */
.word TIMER50_IRQHandler /* Vector Number 186,TIMER50 */
.word TIMER51_IRQHandler /* Vector Number 187,TIMER51 */
.word USBHS1_EP1_OUT_IRQHandler /* Vector Number 188,USBHS1 endpoint 1 out */
.word USBHS1_EP1_IN_IRQHandler /* Vector Number 189,USBHS1 endpoint 1 in */
.word USBHS1_WKUP_IRQHandler /* Vector Number 190,USBHS1 wakeup */
.word USBHS1_IRQHandler /* Vector Number 191,USBHS1 */
.word ENET1_IRQHandler /* Vector Number 192,Ethernet1 */
.word ENET1_WKUP_IRQHandler /* Vector Number 193,Ethernet1 wakeup */
.word 0 /* Reserved */
.word CAN0_WKUP_IRQHandler /* Vector Number 195,CAN0 wakeup */
.word CAN0_Message_IRQHandler /* Vector Number 196,CAN0 interrupt for message buffer */
.word CAN0_Busoff_IRQHandler /* Vector Number 197,CAN0 interrupt for Bus off / Bus off done */
.word CAN0_Error_IRQHandler /* Vector Number 198,CAN0 interrupt for Error */
.word CAN0_FastError_IRQHandler /* Vector Number 199,CAN0 interrupt for Error in fast transmission */
.word CAN0_TEC_IRQHandler /* Vector Number 200,CAN0 interrupt for Transmit warning */
.word CAN0_REC_IRQHandler /* Vector Number 201,CAN0 interrupt for Receive warning */
.word CAN1_WKUP_IRQHandler /* Vector Number 202,CAN1 wakeup */
.word CAN1_Message_IRQHandler /* Vector Number 203,CAN1 interrupt for message buffer */
.word CAN1_Busoff_IRQHandler /* Vector Number 204,CAN1 interrupt for Bus off / Bus off done */
.word CAN1_Error_IRQHandler /* Vector Number 205,CAN1 interrupt for Error */
.word CAN1_FastError_IRQHandler /* Vector Number 206,CAN1 interrupt for Error in fast transmission */
.word CAN1_TEC_IRQHandler /* Vector Number 207,CAN1 interrupt for Transmit warning */
.word CAN1_REC_IRQHandler /* Vector Number 208,CAN1 interrupt for Receive warning */
.word CAN2_WKUP_IRQHandler /* Vector Number 209,CAN2 wakeup */
.word CAN2_Message_IRQHandler /* Vector Number 210,CAN2 interrupt for message buffer */
.word CAN2_Busoff_IRQHandler /* Vector Number 211,CAN2 interrupt for Bus off / Bus off done */
.word CAN2_Error_IRQHandler /* Vector Number 212,CAN2 interrupt for Error */
.word CAN2_FastError_IRQHandler /* Vector Number 213,CAN2 interrupt for Error in fast transmission */
.word CAN2_TEC_IRQHandler /* Vector Number 214,CAN2 interrupt for Transmit warning */
.word CAN2_REC_IRQHandler /* Vector Number 215,CAN2 interrupt for Receive warning */
.word EFUSE_IRQHandler /* Vector Number 216,EFUSE */
.word I2C0_WKUP_IRQHandler /* Vector Number 217,I2C0 wakeup */
.word I2C1_WKUP_IRQHandler /* Vector Number 218,I2C1 wakeup */
.word I2C2_WKUP_IRQHandler /* Vector Number 219,I2C2 wakeup */
.word I2C3_WKUP_IRQHandler /* Vector Number 220,I2C3 wakeup */
.word LPDTS_IRQHandler /* Vector Number 221,LPDTS */
.word LPDTS_WKUP_IRQHandler /* Vector Number 222,LPDTS wakeup */
.word TIMER0_DEC_IRQHandler /* Vector Number 223,TIMER0 DEC */
.word TIMER7_DEC_IRQHandler /* Vector Number 224,TIMER7 DEC */
.word TIMER1_DEC_IRQHandler /* Vector Number 225,TIMER1 DEC */
.word TIMER2_DEC_IRQHandler /* Vector Number 226,TIMER2 DEC */
.word TIMER3_DEC_IRQHandler /* Vector Number 227,TIMER3 DEC */
.word TIMER4_DEC_IRQHandler /* Vector Number 228,TIMER4 DEC */
.word TIMER22_DEC_IRQHandler /* Vector Number 229,TIMER22 DEC */
.word TIMER23_DEC_IRQHandler /* Vector Number 230,TIMER23 DEC */
.word TIMER30_DEC_IRQHandler /* Vector Number 231,TIMER30 DEC */
.word TIMER31_DEC_IRQHandler /* Vector Number 232,TIMER31 DEC */
.size __gVectors, . - __gVectors
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDGT_IRQHandler
.thumb_set WWDGT_IRQHandler,Default_Handler
.weak AVD_LVD_OVD_IRQHandler
.thumb_set AVD_LVD_OVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_LXTAL_IRQHandler
.thumb_set TAMPER_STAMP_LXTAL_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak RCU_IRQHandler
.thumb_set RCU_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA0_Channel0_IRQHandler
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
.weak DMA0_Channel1_IRQHandler
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
.weak DMA0_Channel2_IRQHandler
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
.weak DMA0_Channel3_IRQHandler
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
.weak DMA0_Channel4_IRQHandler
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
.weak DMA0_Channel5_IRQHandler
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
.weak DMA0_Channel6_IRQHandler
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
.weak ADC0_1_IRQHandler
.thumb_set ADC0_1_IRQHandler,Default_Handler
.weak EXTI5_9_IRQHandler
.thumb_set EXTI5_9_IRQHandler,Default_Handler
.weak TIMER0_BRK_IRQHandler
.thumb_set TIMER0_BRK_IRQHandler,Default_Handler
.weak TIMER0_UP_IRQHandler
.thumb_set TIMER0_UP_IRQHandler,Default_Handler
.weak TIMER0_TRG_CMT_IRQHandler
.thumb_set TIMER0_TRG_CMT_IRQHandler,Default_Handler
.weak TIMER0_Channel_IRQHandler
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
.weak TIMER1_IRQHandler
.thumb_set TIMER1_IRQHandler,Default_Handler
.weak TIMER2_IRQHandler
.thumb_set TIMER2_IRQHandler,Default_Handler
.weak TIMER3_IRQHandler
.thumb_set TIMER3_IRQHandler,Default_Handler
.weak I2C0_EV_IRQHandler
.thumb_set I2C0_EV_IRQHandler,Default_Handler
.weak I2C0_ER_IRQHandler
.thumb_set I2C0_ER_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI0_IRQHandler
.thumb_set SPI0_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART0_IRQHandler
.thumb_set USART0_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI10_15_IRQHandler
.thumb_set EXTI10_15_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIMER7_BRK_IRQHandler
.thumb_set TIMER7_BRK_IRQHandler,Default_Handler
.weak TIMER7_UP_IRQHandler
.thumb_set TIMER7_UP_IRQHandler,Default_Handler
.weak TIMER7_TRG_CMT_IRQHandler
.thumb_set TIMER7_TRG_CMT_IRQHandler,Default_Handler
.weak TIMER7_Channel_IRQHandler
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
.weak DMA0_Channel7_IRQHandler
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
.weak EXMC_IRQHandler
.thumb_set EXMC_IRQHandler,Default_Handler
.weak SDIO0_IRQHandler
.thumb_set SDIO0_IRQHandler,Default_Handler
.weak TIMER4_IRQHandler
.thumb_set TIMER4_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak UART3_IRQHandler
.thumb_set UART3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak TIMER5_DAC_UDR_IRQHandler
.thumb_set TIMER5_DAC_UDR_IRQHandler,Default_Handler
.weak TIMER6_IRQHandler
.thumb_set TIMER6_IRQHandler,Default_Handler
.weak DMA1_Channel0_IRQHandler
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak ENET0_IRQHandler
.thumb_set ENET0_IRQHandler,Default_Handler
.weak ENET0_WKUP_IRQHandler
.thumb_set ENET0_WKUP_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak USART5_IRQHandler
.thumb_set USART5_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak USBHS0_EP1_OUT_IRQHandler
.thumb_set USBHS0_EP1_OUT_IRQHandler,Default_Handler
.weak USBHS0_EP1_IN_IRQHandler
.thumb_set USBHS0_EP1_IN_IRQHandler,Default_Handler
.weak USBHS0_WKUP_IRQHandler
.thumb_set USBHS0_WKUP_IRQHandler,Default_Handler
.weak USBHS0_IRQHandler
.thumb_set USBHS0_IRQHandler,Default_Handler
.weak DCI_IRQHandler
.thumb_set DCI_IRQHandler,Default_Handler
.weak CAU_IRQHandler
.thumb_set CAU_IRQHandler,Default_Handler
.weak HAU_TRNG_IRQHandler
.thumb_set HAU_TRNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART6_IRQHandler
.thumb_set UART6_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SAI0_IRQHandler
.thumb_set SAI0_IRQHandler,Default_Handler
.weak TLI_IRQHandler
.thumb_set TLI_IRQHandler,Default_Handler
.weak TLI_ER_IRQHandler
.thumb_set TLI_ER_IRQHandler,Default_Handler
.weak IPA_IRQHandler
.thumb_set IPA_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak OSPI0_IRQHandler
.thumb_set OSPI0_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak RSPDIF_IRQHandler
.thumb_set RSPDIF_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak HPDF_INT0_IRQHandler
.thumb_set HPDF_INT0_IRQHandler,Default_Handler
.weak HPDF_INT1_IRQHandler
.thumb_set HPDF_INT1_IRQHandler,Default_Handler
.weak HPDF_INT2_IRQHandler
.thumb_set HPDF_INT2_IRQHandler,Default_Handler
.weak HPDF_INT3_IRQHandler
.thumb_set HPDF_INT3_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak TIMER14_IRQHandler
.thumb_set TIMER14_IRQHandler,Default_Handler
.weak TIMER15_IRQHandler
.thumb_set TIMER15_IRQHandler,Default_Handler
.weak TIMER16_IRQHandler
.thumb_set TIMER16_IRQHandler,Default_Handler
.weak MDIO_IRQHandler
.thumb_set MDIO_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDIO1_IRQHandler
.thumb_set SDIO1_IRQHandler,Default_Handler
.weak HWSEM_IRQHandler
.thumb_set HWSEM_IRQHandler,Default_Handler
.weak ADC2_IRQHandler
.thumb_set ADC2_IRQHandler,Default_Handler
.weak CMP0_1_IRQHandler
.thumb_set CMP0_1_IRQHandler,Default_Handler
.weak CTC_IRQHandler
.thumb_set CTC_IRQHandler,Default_Handler
.weak RAMECCMU_IRQHandler
.thumb_set RAMECCMU_IRQHandler,Default_Handler
.weak OSPI1_IRQHandler
.thumb_set OSPI1_IRQHandler,Default_Handler
.weak RTDEC0_IRQHandler
.thumb_set RTDEC0_IRQHandler,Default_Handler
.weak RTDEC1_IRQHandler
.thumb_set RTDEC1_IRQHandler,Default_Handler
.weak FAC_IRQHandler
.thumb_set FAC_IRQHandler,Default_Handler
.weak TMU_IRQHandler
.thumb_set TMU_IRQHandler,Default_Handler
.weak TIMER22_IRQHandler
.thumb_set TIMER22_IRQHandler,Default_Handler
.weak TIMER23_IRQHandler
.thumb_set TIMER23_IRQHandler,Default_Handler
.weak TIMER30_IRQHandler
.thumb_set TIMER30_IRQHandler,Default_Handler
.weak TIMER31_IRQHandler
.thumb_set TIMER31_IRQHandler,Default_Handler
.weak TIMER40_IRQHandler
.thumb_set TIMER40_IRQHandler,Default_Handler
.weak TIMER41_IRQHandler
.thumb_set TIMER41_IRQHandler,Default_Handler
.weak TIMER42_IRQHandler
.thumb_set TIMER42_IRQHandler,Default_Handler
.weak TIMER43_IRQHandler
.thumb_set TIMER43_IRQHandler,Default_Handler
.weak TIMER44_IRQHandler
.thumb_set TIMER44_IRQHandler,Default_Handler
.weak TIMER50_IRQHandler
.thumb_set TIMER50_IRQHandler,Default_Handler
.weak TIMER51_IRQHandler
.thumb_set TIMER51_IRQHandler,Default_Handler
.weak USBHS1_EP1_OUT_IRQHandler
.thumb_set USBHS1_EP1_OUT_IRQHandler,Default_Handler
.weak USBHS1_EP1_IN_IRQHandler
.thumb_set USBHS1_EP1_IN_IRQHandler,Default_Handler
.weak USBHS1_WKUP_IRQHandler
.thumb_set USBHS1_WKUP_IRQHandler,Default_Handler
.weak USBHS1_IRQHandler
.thumb_set USBHS1_IRQHandler,Default_Handler
.weak ENET1_IRQHandler
.thumb_set ENET1_IRQHandler,Default_Handler
.weak ENET1_WKUP_IRQHandler
.thumb_set ENET1_WKUP_IRQHandler,Default_Handler
.weak CAN0_WKUP_IRQHandler
.thumb_set CAN0_WKUP_IRQHandler,Default_Handler
.weak CAN0_Message_IRQHandler
.thumb_set CAN0_Message_IRQHandler,Default_Handler
.weak CAN0_Busoff_IRQHandler
.thumb_set CAN0_Busoff_IRQHandler,Default_Handler
.weak CAN0_Error_IRQHandler
.thumb_set CAN0_Error_IRQHandler,Default_Handler
.weak CAN0_FastError_IRQHandler
.thumb_set CAN0_FastError_IRQHandler,Default_Handler
.weak CAN0_TEC_IRQHandler
.thumb_set CAN0_TEC_IRQHandler,Default_Handler
.weak CAN0_REC_IRQHandler
.thumb_set CAN0_REC_IRQHandler,Default_Handler
.weak CAN1_WKUP_IRQHandler
.thumb_set CAN1_WKUP_IRQHandler,Default_Handler
.weak CAN1_Message_IRQHandler
.thumb_set CAN1_Message_IRQHandler,Default_Handler
.weak CAN1_Busoff_IRQHandler
.thumb_set CAN1_Busoff_IRQHandler,Default_Handler
.weak CAN1_Error_IRQHandler
.thumb_set CAN1_Error_IRQHandler,Default_Handler
.weak CAN1_FastError_IRQHandler
.thumb_set CAN1_FastError_IRQHandler,Default_Handler
.weak CAN1_TEC_IRQHandler
.thumb_set CAN1_TEC_IRQHandler,Default_Handler
.weak CAN1_REC_IRQHandler
.thumb_set CAN1_REC_IRQHandler,Default_Handler
.weak CAN2_WKUP_IRQHandler
.thumb_set CAN2_WKUP_IRQHandler,Default_Handler
.weak CAN2_Message_IRQHandler
.thumb_set CAN2_Message_IRQHandler,Default_Handler
.weak CAN2_Busoff_IRQHandler
.thumb_set CAN2_Busoff_IRQHandler,Default_Handler
.weak CAN2_Error_IRQHandler
.thumb_set CAN2_Error_IRQHandler,Default_Handler
.weak CAN2_FastError_IRQHandler
.thumb_set CAN2_FastError_IRQHandler,Default_Handler
.weak CAN2_TEC_IRQHandler
.thumb_set CAN2_TEC_IRQHandler,Default_Handler
.weak CAN2_REC_IRQHandler
.thumb_set CAN2_REC_IRQHandler,Default_Handler
.weak EFUSE_IRQHandler
.thumb_set EFUSE_IRQHandler,Default_Handler
.weak I2C0_WKUP_IRQHandler
.thumb_set I2C0_WKUP_IRQHandler,Default_Handler
.weak I2C1_WKUP_IRQHandler
.thumb_set I2C1_WKUP_IRQHandler,Default_Handler
.weak I2C2_WKUP_IRQHandler
.thumb_set I2C2_WKUP_IRQHandler,Default_Handler
.weak I2C3_WKUP_IRQHandler
.thumb_set I2C3_WKUP_IRQHandler,Default_Handler
.weak LPDTS_IRQHandler
.thumb_set LPDTS_IRQHandler,Default_Handler
.weak LPDTS_WKUP_IRQHandler
.thumb_set LPDTS_WKUP_IRQHandler,Default_Handler
.weak TIMER0_DEC_IRQHandler
.thumb_set TIMER0_DEC_IRQHandler,Default_Handler
.weak TIMER7_DEC_IRQHandler
.thumb_set TIMER7_DEC_IRQHandler,Default_Handler
.weak TIMER1_DEC_IRQHandler
.thumb_set TIMER1_DEC_IRQHandler,Default_Handler
.weak TIMER2_DEC_IRQHandler
.thumb_set TIMER2_DEC_IRQHandler,Default_Handler
.weak TIMER3_DEC_IRQHandler
.thumb_set TIMER3_DEC_IRQHandler,Default_Handler
.weak TIMER4_DEC_IRQHandler
.thumb_set TIMER4_DEC_IRQHandler,Default_Handler
.weak TIMER22_DEC_IRQHandler
.thumb_set TIMER22_DEC_IRQHandler,Default_Handler
.weak TIMER23_DEC_IRQHandler
.thumb_set TIMER23_DEC_IRQHandler,Default_Handler
.weak TIMER30_DEC_IRQHandler
.thumb_set TIMER30_DEC_IRQHandler,Default_Handler
.weak TIMER31_DEC_IRQHandler
.thumb_set TIMER31_DEC_IRQHandler,Default_Handler
Firmware/CMSIS/GD/GD32H7xx/Source/IAR/startup_gd32h7xx.s
+1158
View File
File diff suppressed because it is too large Load Diff
Firmware/CMSIS/GD/GD32H7xx/Source/system_gd32h7xx.c
+891
View File
@@ -0,0 +1,891 @@
/*!
\file system_gd32h7xx.c
\brief CMSIS Cortex-M7 Device Peripheral Access Layer Source File for
gd32h7xx Device Series
*/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
* Copyright (c) 2025, GigaDevice Semiconductor Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#include "gd32h7xx.h"
/* system frequency define */
#define __IRC64M (IRC64M_VALUE) /* internal 64 MHz RC oscillator frequency */
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
#define __LPIRC4M (LPIRC4M_VALUE) /* low power internal 4 MHz RC oscillator frequency */
#define __SYS_OSC_CLK (__IRC64M) /* main oscillator frequency */
#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
#define RCU_APB4EN_SYSCFG (uint32_t)0x01 /* enable SYSCFG clk */
/* select a system clock by uncommenting the following line */
/* use IRC64M */
//#define __SYSTEM_CLOCK_IRC64M (__IRC64M)
//#define __SYSTEM_CLOCK_480M_PLL0_IRC64M (uint32_t)(480000000)
//#define __SYSTEM_CLOCK_600M_PLL0_IRC64M (uint32_t)(600000000)
/* use LPIRC4M */
//#define __SYSTEM_CLOCK_LPIRC4M (__LPIRC4M)
/* use HXTAL(CK_HXTAL = 25M) */
//#define __SYSTEM_CLOCK_HXTAL (__HXTAL)
//#define __SYSTEM_CLOCK_200M_PLL0_HXTAL (uint32_t)(200000000)
//#define __SYSTEM_CLOCK_400M_PLL0_HXTAL (uint32_t)(400000000)
//#define __SYSTEM_CLOCK_480M_PLL0_HXTAL (uint32_t)(480000000)
#define __SYSTEM_CLOCK_600M_PLL0_HXTAL (uint32_t)(600000000)
/*
Note: the power mode need to match the mcu selection and external power supply circuit.
for iar project:
for 100-pin mcu, need to define macro GD32H7XXV.
for 144-pin mcu, need to define macro GD32H7XXZ.
for 176-pin mcu, need to define macro GD32H7XXI.
for keil project:
do not need to define these macros extra.
according to the selected mcu and external power supply circuit to uncomment
the following macro SEL_PMU_SMPS_MODE.
*/
#if defined(GD32H7XXI)
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_DIRECT_SMPS_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_BYPASS
#elif defined(GD32H7XXZ) | defined(GD32H7XXV)
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_BYPASS
#endif
#define SEL_IRC64MDIV 0x00U
#define SEL_HXTAL 0x01U
#define SEL_LPIRC4M 0x02U
#define SEL_PLL0P 0x03U
#define PLL0PSC_REG_OFFSET 0U
#define PLL0N_REG_OFFSET 6U
#define PLL0P_REG_OFFSET 16U
#define PLL0Q_REG_OFFSET 0U
#define PLL0R_REG_OFFSET 24U
/* set the system clock frequency and declare the system clock configuration function */
#ifdef __SYSTEM_CLOCK_IRC64M
uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC64M;
static void system_clock_64m_irc64m(void);
#elif defined (__SYSTEM_CLOCK_480M_PLL0_IRC64M)
#define PLL0PSC 16U
#define PLL0N (120U - 1U)
#define PLL0P (1U - 1U)
#define PLL0Q (2U - 1U)
#define PLL0R (2U - 1U)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_480M_PLL0_IRC64M;
static void system_clock_480m_irc64m(void);
#elif defined (__SYSTEM_CLOCK_600M_PLL0_IRC64M)
#define PLL0PSC 16U
#define PLL0N (150U - 1U)
#define PLL0P (1U - 1U)
#define PLL0Q (2U - 1U)
#define PLL0R (2U - 1U)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_600M_PLL0_IRC64M;
static void system_clock_600m_irc64m(void);
#elif defined (__SYSTEM_CLOCK_LPIRC4M)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_LPIRC4M;
static void system_clock_4m_lpirc4m(void);
#elif defined (__SYSTEM_CLOCK_HXTAL)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
static void system_clock_hxtal(void);
#elif defined (__SYSTEM_CLOCK_200M_PLL0_HXTAL)
#define PLL0PSC 5U
#define PLL0N (40U - 1U)
#define PLL0P (1U - 1U)
#define PLL0Q (2U - 1U)
#define PLL0R (2U - 1U)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL0_HXTAL;
static void system_clock_200m_hxtal(void);
#elif defined (__SYSTEM_CLOCK_400M_PLL0_HXTAL)
#define PLL0PSC 5U
#define PLL0N (80U - 1U)
#define PLL0P (1U - 1U)
#define PLL0Q (2U - 1U)
#define PLL0R (2U - 1U)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_400M_PLL0_HXTAL;
static void system_clock_400m_hxtal(void);
#elif defined (__SYSTEM_CLOCK_480M_PLL0_HXTAL)
#define PLL0PSC 5U
#define PLL0N (96U - 1U)
#define PLL0P (1U - 1U)
#define PLL0Q (2U - 1U)
#define PLL0R (2U - 1U)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_480M_PLL0_HXTAL;
static void system_clock_480m_hxtal(void);
#elif defined (__SYSTEM_CLOCK_600M_PLL0_HXTAL)
#define PLL0PSC 5U
#define PLL0N (120U - 1U)
#define PLL0P (1U - 1U)
#define PLL0Q (2U - 1U)
#define PLL0R (2U - 1U)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_600M_PLL0_HXTAL;
static void system_clock_600m_hxtal(void);
#endif /* __SYSTEM_CLOCK_IRC64M */
/* configure the system clock */
static void system_clock_config(void);
/*!
\brief setup the microcontroller system, initialize the system
\param[in] none
\param[out] none
\retval none
*/
void SystemInit(void)
{
/* FPU settings */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1U)
/* set CP10 and CP11 Full Access */
SCB->CPACR |= (uint32_t)((0x03U << 10U * 2U) | (0x03U << 11U * 2U));
#endif
SCB_EnableDCache();
SCB_DisableDCache();
/* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN;
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
}
/* no TCM wait state */
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
SYSCFG_SRAMCFG1 &= ~SYSCFG_SRAMCFG1_TCM_WAITSTATE;
RCU_CFG0 &= ~RCU_CFG0_SCS;
/* reset RCU */
/* reset HXTALEN, CKMEN, PLL0EN, PLL1EN, PLL2EN, PLLUSB0 and PLLUSB1 bits */
RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLL0EN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_HXTALBPS);
RCU_ADDCTL1 &= ~(RCU_ADDCTL1_PLLUSBHS0EN | RCU_ADDCTL1_PLLUSBHS1EN | RCU_ADDCTL1_LPIRC4MEN);
/* reset CFG0, CFG1, CFG2, CFG3 registers */
RCU_CFG0 &= ~(RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_APB3PSC | RCU_CFG0_APB4PSC | RCU_CFG0_AHBPSC |
RCU_CFG0_I2C0SEL | RCU_CFG0_SCS | RCU_CFG0_RTCDIV);
RCU_CFG1 &= ~(RCU_CFG1_HPDFSEL | RCU_CFG1_TIMERSEL | RCU_CFG1_PERSEL |
RCU_CFG1_RSPDIFSEL | RCU_CFG1_USART0SEL | RCU_CFG1_USART1SEL | RCU_CFG1_USART2SEL | RCU_CFG1_USART5SEL | RCU_CFG1_PLL2RDIV);
RCU_CFG2 &= ~(RCU_CFG2_SAI2B1SEL | RCU_CFG2_SAI2B0SEL | RCU_CFG2_SAI1SEL | RCU_CFG2_SAI0SEL |
RCU_CFG2_CKOUT0SEL | RCU_CFG2_CKOUT1SEL | RCU_CFG2_CKOUT0DIV | RCU_CFG2_CKOUT1DIV);
RCU_CFG3 &= ~(RCU_CFG3_ADC01SEL | RCU_CFG3_ADC2SEL | RCU_CFG3_SDIO1SEL
| RCU_CFG3_I2C3SEL | RCU_CFG3_I2C2SEL | RCU_CFG3_I2C1SEL);
RCU_CFG4 &= ~(RCU_CFG4_EXMCSEL | RCU_CFG4_SDIO0SEL);
RCU_CFG5 &= ~(RCU_CFG5_SPI0SEL | RCU_CFG5_SPI1SEL | RCU_CFG5_SPI2SEL |
RCU_CFG5_SPI3SEL | RCU_CFG5_SPI4SEL | RCU_CFG5_SPI5SEL);
/* disable all interrupts */
RCU_INT = 0x14FF0000U;
RCU_ADDINT = 0x00700000U;
/* reset all PLL0 parameter */
RCU_PLL0 = 0x01002020U;
RCU_PLL1 = 0x01012020U;
RCU_PLL2 = 0x01012020U;
RCU_PLLALL = 0x00000000U;
RCU_PLLADDCTL = 0x00010101U;
RCU_PLLUSBCFG = 0x00000000U;
RCU_PLL0FRA = 0x00000000U;
RCU_PLL1FRA = 0x00000000U;
RCU_PLL2FRA = 0x00000000U;
#if defined (SEL_PMU_SMPS_MODE)
/* power supply config */
pmu_smps_ldo_supply_config(SEL_PMU_SMPS_MODE);
#endif
/* configure system clock */
system_clock_config();
#ifdef VECT_TAB_SRAM
nvic_vector_table_set(NVIC_VECTTAB_RAM, VECT_TAB_OFFSET);
#else
nvic_vector_table_set(NVIC_VECTTAB_FLASH, VECT_TAB_OFFSET);
#endif
}
/*!
\brief configure the system clock
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_config(void)
{
#ifdef __SYSTEM_CLOCK_IRC64M
system_clock_64m_irc64m();
#elif defined (__SYSTEM_CLOCK_480M_PLL0_IRC64M)
system_clock_480m_irc64m();
#elif defined (__SYSTEM_CLOCK_600M_PLL0_IRC64M)
system_clock_600m_irc64m();
#elif defined (__SYSTEM_CLOCK_LPIRC4M)
system_clock_4m_lpirc4m();
#elif defined (__SYSTEM_CLOCK_HXTAL)
system_clock_hxtal();
#elif defined (__SYSTEM_CLOCK_200M_PLL0_HXTAL)
system_clock_200m_hxtal();
#elif defined (__SYSTEM_CLOCK_400M_PLL0_HXTAL)
system_clock_400m_hxtal();
#elif defined (__SYSTEM_CLOCK_480M_PLL0_HXTAL)
system_clock_480m_hxtal();
#elif defined (__SYSTEM_CLOCK_600M_PLL0_HXTAL)
system_clock_600m_hxtal();
#endif /* __SYSTEM_CLOCK_IRC64M */
}
#ifdef __SYSTEM_CLOCK_IRC64M
/*!
\brief configure the system clock to 64M by IRC64M
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_64m_irc64m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN;
/* wait until IRC64M is stable or the startup time is longer than IRC64M_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC64MSTB);
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(1) {
}
}
/* AHB = SYSCLK / 1 */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB4 = AHB / 1 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV1;
/* APB3 = AHB / 1 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV1;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 1 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* configure IRC64M div */
RCU_ADDCTL1 &= ~(RCU_ADDCTL1_IRC64MDIV);
RCU_ADDCTL1 |= RCU_IRC64M_DIV1;
/* select IRC64M as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_IRC64MDIV;
/* wait until IRC64M is selected as system clock */
while(RCU_SCSS_IRC64MDIV != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#elif defined (__SYSTEM_CLOCK_480M_PLL0_IRC64M)
/*!
\brief configure the system clock to 480M by PLL0 which selects IRC64M as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_480m_irc64m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN;
/* wait until IRC64M is stable or the startup time is longer than IRC64M_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC64MSTB);
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(1) {
}
}
/* insert TCM wait state at 480MHz */
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
/* IRC64M is already stable */
/* AHB = SYSCLK / 2 */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
/* APB4 = AHB / 2 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
/* APB3 = AHB / 2 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* PLL0 select IRC64MDIV, config IRC64MDIV as IRC64M, PLL0 input and output range */
RCU_ADDCTL1 &= ~(RCU_ADDCTL1_IRC64MDIV);
RCU_ADDCTL1 |= RCU_IRC64M_DIV1;
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
RCU_PLLALL |= (RCU_PLLSRC_IRC64MDIV | RCU_PLL0RNG_4M_8M);
/* PLL0P = IRC64MDIV / 16 * 120 / 1 = 480 MHz */
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
/* enable PLL0P, PLL0Q, PLL0R */
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
/* enable PLL0 */
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
}
/* select PLL0 as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#elif defined (__SYSTEM_CLOCK_600M_PLL0_IRC64M)
/*!
\brief configure the system clock to 600M by PLL0 which selects IRC64M as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_600m_irc64m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN;
/* wait until IRC64M is stable or the startup time is longer than IRC64M_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC64MSTB);
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(1) {
}
}
/* insert TCM wait state at 600MHz */
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
/* IRC64M is already stable */
/* AHB = SYSCLK / 2 */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
/* APB4 = AHB / 2 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
/* APB3 = AHB / 2 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* PLL0 select IRC64MDIV, config IRC64MDIV as IRC64M, PLL0 input and output range */
RCU_ADDCTL1 &= ~(RCU_ADDCTL1_IRC64MDIV);
RCU_ADDCTL1 |= RCU_IRC64M_DIV1;
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
RCU_PLLALL |= (RCU_PLLSRC_IRC64MDIV | RCU_PLL0RNG_4M_8M);
/* PLL0P = IRC64MDIV / 16 * 150 / 1 = 600 MHz */
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
/* enable PLL0P, PLL0Q, PLL0R */
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
/* enable PLL0 */
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
}
/* select PLL0 as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#elif defined (__SYSTEM_CLOCK_LPIRC4M)
/*!
\brief configure the system clock to LPIRC4M
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_4m_lpirc4m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable LPIRC4M */
RCU_ADDCTL1 |= RCU_ADDCTL1_LPIRC4MEN;
/* wait until LPIRC4M is stable or the startup time is longer than LPIRC4M_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB);
} while((0U == stab_flag) && (LPIRC4M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB)) {
while(1) {
}
}
/* LPIRC4M is stable */
/* AHB = SYSCLK / 1*/
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB4 = AHB / 1 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV1;
/* APB3 = AHB / 1 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV1;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 1 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* select LPIRC4M as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_LPIRC4M;
/* wait until LPIRC4M is selected as system clock */
while(RCU_SCSS_LPIRC4M != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#elif defined (__SYSTEM_CLOCK_HXTAL)
/*!
\brief configure the system clock to HXTAL
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
}
}
/* HXTAL is stable */
/* AHB = SYSCLK / 1*/
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB4 = AHB / 1 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV1;
/* APB3 = AHB / 1 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV1;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 1 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* select HXTAL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
/* wait until HXTAL is selected as system clock */
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#elif defined (__SYSTEM_CLOCK_200M_PLL0_HXTAL)
/*!
\brief configure the system clock to 200M by PLL0 which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_200m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
}
}
/* HXTAL is stable */
/* AHB = SYSCLK / 1 */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB4 = AHB / 2 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
/* APB3 = AHB / 2 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* PLL0 select HXTAL, configure PLL0 input and output range */
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
RCU_PLLALL |= (RCU_PLLSRC_HXTAL | RCU_PLLALL_PLL0VCOSEL | RCU_PLL0RNG_4M_8M);
/* PLL0P = HXTAL / 5 * 40 = 200 MHz */
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
/* enable PLL0P, PLL0Q, PLL0R */
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
/* enable PLL0 */
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
}
/* select PLL0 as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#elif defined (__SYSTEM_CLOCK_400M_PLL0_HXTAL)
/*!
\brief configure the system clock to 400M by PLL0 which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_400m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
}
}
/* insert TCM wait state at 400MHz */
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
/* HXTAL is stable */
/* AHB = SYSCLK / 1 */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
/* APB4 = AHB / 2 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
/* APB3 = AHB / 2 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* PLL0 select HXTAL, configure PLL0 input and output range */
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
RCU_PLLALL |= (RCU_PLLSRC_HXTAL | RCU_PLLALL_PLL0VCOSEL | RCU_PLL0RNG_4M_8M);
/* PLL0P = HXTAL / 5 * 80 = 400 MHz */
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
/* enable PLL0P, PLL0Q, PLL0R */
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
/* enable PLL */
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
}
/* select PLL0 as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#elif defined (__SYSTEM_CLOCK_480M_PLL0_HXTAL)
/*!
\brief configure the system clock to 480M by PLL0 which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_480m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
}
}
/* insert TCM wait state at 480MHz */
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
/* HXTAL is stable */
/* AHB = SYSCLK / 2 */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
/* APB4 = AHB / 2 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
/* APB3 = AHB / 2 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* PLL select HXTAL, configure PLL input and output range */
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
RCU_PLLALL |= (RCU_PLLSRC_HXTAL | RCU_PLL0RNG_4M_8M);
/* PLL0P = HXTAL / 5 * 96 = 480 MHz */
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
/* enable PLL0P, PLL0Q, PLL0R */
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
/* enable PLL0 */
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
}
/* select PLL0 as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#elif defined (__SYSTEM_CLOCK_600M_PLL0_HXTAL)
/*!
\brief configure the system clock to 600M by PLL0 which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_600m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
}
}
/* insert TCM wait state at 600MHz */
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
/* HXTAL is stable */
/* AHB = SYSCLK / 2 */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
/* APB4 = AHB / 2 */
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
/* APB3 = AHB / 2 */
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
/* APB2 = AHB / 1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB / 2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* PLL select HXTAL, configure PLL input and output range */
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
RCU_PLLALL |= (RCU_PLLSRC_HXTAL | RCU_PLL0RNG_4M_8M);
/* PLL0P = HXTAL / 5 * 120 = 600 MHz */
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
/* enable PLL0P, PLL0Q, PLL0R */
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
/* enable PLL0 */
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
}
/* select PLL0 as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
}
}
#endif /* __SYSTEM_CLOCK_IRC64M */
/*!
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
\param[in] none
\param[out] none
\retval none
*/
void SystemCoreClockUpdate(void)
{
uint32_t sws = 0U;
uint32_t irc64div = 0U;
uint32_t pllpsc = 0U, plln = 0U, pllp = 0U, pllsel = 0U;
sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws) {
/* IRC64M is selected as CK_SYS */
case SEL_IRC64MDIV:
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
SystemCoreClock = IRC64M_VALUE / irc64div;
break;
/* HXTAL is selected as CK_SYS */
case SEL_LPIRC4M:
SystemCoreClock = LPIRC4M_VALUE;
break;
/* HXTAL is selected as CK_SYS */
case SEL_HXTAL:
SystemCoreClock = HXTAL_VALUE;
break;
/* PLL0P is selected as CK_SYS */
case SEL_PLL0P:
/* get the value of PLL0PSC[0,5], PLL0N[6,14], PLL0P[16,22] */
pllpsc = GET_BITS(RCU_PLL0, 0, 5);
plln = GET_BITS(RCU_PLL0, 6, 14) + 1U;
pllp = GET_BITS(RCU_PLL0, 16, 22) + 1U;
/* PLL clock source selection, HXTAL or IRC64M_VALUE or LPIRC4M_VALUE */
pllsel = GET_BITS(RCU_PLLALL, 16, 17);
if(0U == pllsel) {
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
SystemCoreClock = (IRC64M_VALUE / irc64div / pllpsc) * plln / pllp;
} else if(1U == pllsel) {
SystemCoreClock = (LPIRC4M_VALUE / pllpsc) * plln / pllp;
} else {
SystemCoreClock = (HXTAL_VALUE / pllpsc) * plln / pllp;
}
break;
default:
/* should not be here */
break;
}
}
#ifdef __FIRMWARE_VERSION_DEFINE
/*!
\brief get firmware version
\param[in] none
\param[out] none
\retval firmware version
*/
uint32_t gd32h7xx_firmware_version_get(void)
{
return __GD32H7XX_STDPERIPH_VERSION;
}
#endif /* __FIRMWARE_VERSION_DEFINE */
Firmware/CMSIS/LICENSE.TXT
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Firmware/CMSIS/cachel1_armv7.h
+411
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/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.1
* @date 19. April 2021
******************************************************************************/
/*
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_CACHEL1_ARMV7_H
#define ARM_CACHEL1_ARMV7_H
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#ifndef __SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief I-Cache Invalidate by address
\details Invalidates I-Cache for the given address.
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
I-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address.
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#endif /* ARM_CACHEL1_ARMV7_H */
Firmware/CMSIS/cmsis_compiler.h
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
Firmware/CMSIS/cmsis_gcc.h
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Firmware/CMSIS/cmsis_version.h
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
Firmware/CMSIS/core_cm7.h
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Firmware/CMSIS/mpu_armv7.h
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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.2
* @date 25. May 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif